1. Field of the Invention
The present invention relates to a volatile memory which is required to operate with low power, and a volatile memory module of an embedded dynamic random access memory (hereinafter referred to as an eRAM) in which a processor and a memory are provided together, that is, a dynamic random access memory (hereinafter referred to as a DRAM), and more particularly to self-refresh of the volatile memory or the DRAM provided in the eRAM.
2. Description of the Background Art
Recently, memories to be used in a field requiring low power consumption such as portable equipment or the like have also had capacities increased with an advancement of information processing and an increase of information. These memories include a volatile memory such as a DRAM which features a large capacity and space-saving. A reduction in power consumption has been required for the DRAM and the like which are to be used in such a field in the same manner as in apparatus which incorporate them.
With a development of fineness, a microprocessor and a DRAM can be provided together in one chip. Programs and data are stored in a high speed built-in large capacity memory so that a processing can be performed at a high speed. In the following description, an EDRAM includes the microprocessor and the DRAM in one chip.
In some cases where the volatile memory such as the DRAM and the eRAM are incorporated in the above-mentioned portable equipment, programming is performed in consideration of a memory use region such as a program size, a data size or the like in order to increase performance within a range in which a memory size is limited. For this reason, whether or not all regions of the volatile memory such as the DRAM are used depends on programs to be executed.
The contents stored in the volatile memory disappear with the passage of time. Therefore, a refresh operation is required. In particular, it is necessary to generate a control signal timing and a refresh address in the volatile memory in order to hold the stored contents when an operation of a system provided on the periphery of the volatile memory is stopped. For this reason, the volatile memory has a built-in oscillator in such a manner that it can perform a self-refresh operation.
FIG. 8 is a block diagram showing an example of a structure of a conventional DRAM which can perform the self-refresh operation. Since data held in a memory array 2 disappears with the passage of time, a DRAM 1 should operate in various cycles other than a read cycle and a write cycle to perform writing and reading while holding the stored contents. In writing to and reading from the memory array 2, a word line is selected by a row decoder 3, and also a sense amplifier 4 is selected with a row address depending on circumstances. The DRAM 1 includes an internal timing control circuit 5 for generating, in various cycles, internal timing control signals WLE, SAE and the like which are to be sent to each of internal modules such as the row decoder 3 and the sense amplifier 4. Therefore, a row address strobe signal RAS and a column address strobe signal CAS which give a reading timing of an address Ai and a self-refresh signal SRF which gives a self-refresh period are sent from an outside of the DRAM 1 to the internal timing control circuit 5 through an input terminal 13. In order to store data in the DRAM 1, it is necessary to specify a storage location on the memory array 2. For this reason, the address Ai input from the outside to an input terminal 14 is temporarily stored in an address latch 6. A row address Ari in the address Ai stored in the address latch 6 is given to the row decoder 3, and a column address is given to a column decoder. The row address and the column address are decoded by these decoders so that a word line 16 is selectively activated and the sense amplifier 4 or its output is selected. Consequently, data is read from and written to a desired portion of the memory array 2.
Next, a module related to the self-refresh will be described. A refresh interval at which the self-refresh is to be performed is determined by an oscillator 10. The oscillator 10 is on-off controlled in response to an operating mode signal Mode. The operating mode signal Mode is determined on the basis of a control signal group sent from the outside of the DRAM 1 to the input terminal 13, for example, RAS, CAS, SRF and the like. An output intC of the oscillator 10 is input, to the internal timing control circuit 5, as a trigger of an internal timing control signal output from the internal timing control circuit 5 when the self-refresh is performed.
A refresh address is generated by a refresh address generating circuit 11 formed by a counter. A timing for generating the refresh address is determined in response to an address control signal Sac sent from the internal timing control circuit 5. A count value of the address control signal Sac acts as a refresh address RAi, for example. In the refresh address generating circuit 11, a count of the address control signal Sac means address generation and means self-refresh termination of all memory cells which require counter resetting to be performed when the count value reaches a predetermined value.
The refresh address RAi generated by the refresh address generating circuit 11 is selected by an address selecting circuit 12 according to the address control signal Sac, and is transmitted to the row decoder 3. Thus, a memory cell connected to the word line 16 which is selected with the refresh address RAi is refreshed.
The above refresh operation will be summarized. The refresh address RAi is generated in a cycle of the output intC of the oscillator 10. The word line 16 is caused to sequentially rise with the refresh address RAi. Rewriting is performed by the sense amplifier 4 so that the contents of the memory array 2 are held.
The volatile memory or the eRAM including the volatile memory module according to the prior art has the above-mentioned structure. These memories are often utilized for various purposes. Therefore, whether or not internal regions of the memories are utilized for actual programs, the self-refresh is uniformly performed. The self-refresh is different from CBR (CAS before RAS) refresh and the like, for example. Once a self-refresh mode is started, an operation is independently performed by using the internal oscillator. For this reason, a portion which does not need to be self-refreshed is refreshed in the same manner as a portion which should be self-refreshed. Consequently, power is wastefully consumed due to the refresh operation in the portion which does not need to be self-refreshed.